1. Field of the Invention
The present invention relates to a method for forming CMOS transistors having matching characteristics and the apparatus formed by the method. More particularly, the present invention relates to a method for forming the CMOS transistors in the (111) surface plane and enabling a velocity saturation of both transistors.
2. Description of the Related Art
Historically, (111) surface orientation wafers were the first mass produced for use in integrated circuit technology. Such orientations are the easiest and least expensive to produce and were still used until recently in bipolar circuit tecnology. Around 1970, however, MOS (xe2x80x9cmetal oxide semiconductorxe2x80x9d) technology changed to the currently used (100) surface orientation of the wafers. This change was made when NMOS (xe2x80x9cn channel MOSFETxe2x80x9d) technology rather than PMOS (xe2x80x9cp channel MOSFETxe2x80x9d) technology became common and before the advent of CMOS technology. FIGS. 1A-1B illustrate the surface planes (100) and (111) and (110) and  less than 100 greater than  and  less than 111 greater than  and  less than 110 greater than  directions in a cubic crystalline structure, such as silicon, as discussed above, and FIG. 1C lists the relative number of atoms/unit area, the typical surface state densities and oxide charges, and the normal region of operation of surface-hole mobility of the different surfaces when employed in MOS technology.
An important development in the late 1960""s was the one-transistor dynamic memory cell used in random access memories (the xe2x80x9cDRAMxe2x80x9d). A typical fabricated DRAM memory cell is pictured in FIG. 2. A DRAM cell, as pictured, is an integrated combination of a charge storage element (a capacitor or pn junction) and a MOSFET used as a switch. As shown in FIG. 2, the DRAM includes an n+drain 10 formed in p-type silicon 12. The capacitor or pn junction 14 is formed to the left of the access transistor 16. Polysilicon-1 18 and polysilicon-2 20 are formed in an intermediate oxide layer 22. An aluminum layer 24 is formed above the intermediate oxide layer 22.
As mentioned above, the 1970""s saw the emergence of NMOS technology as preferred over PMOS technology. Routinely fabricated p-channel MOSFETs constructed in the standard configuration are ideally and practically enhancement mode devices, while n-channel MOSFETs are also ideally enhancement mode devices. However, because non-idealities tend to shift the threshold voltage toward negative biases, early NMOS transistors were typically of the depletion mode type. Until about 1977, this difference led to the domination of PMOS technology, that is, IC""s (xe2x80x9cintegrated circuitsxe2x80x9d) incorporating PMOS technology dominated the commercial marketplace. Subsequently, NMOS gained acceptance as it provides for a greater mobility of electrons relative to holes. NMOS technology is now incorporated into the majority of newly designed IC""s.
The (100) surface orientation for wafers was chosen over the previously used (111) orientation due to its low surface state charge density on thermally oxidized surfaces, that is 9xc3x971010/cm2 versus 5xc3x971011/cm2. This was a particularly important consideration for NMOS technologies, which were gaining favor, in that high surface state charge density makes it more difficult to control active and parasitic device threshold voltages. Parasitic thresholds are no longer a concern with CMOS technology because of the high well dopings and/or channel stop surface implantation used. For (111) surfaces, the surface state charge density is less than 5xc3x971011/cm2, which value is higher than that of the (100) surface. In present day technology, this would amount to less than a 0.25 V offset in active device threshold voltage and is readily compensated by the surface threshold voltage ion implantations.
A further benefit of NMOS devices was that the electron mobility in the inversion layers is greater on the (100) surfaces than on the other low order planes. However, it has been pointed out in U.S. Pat. No. 4,857,986 to Kinugawa that for modern day CMOS technology with sub-micron devices, a different set of tradeoffs exist. In such short-channel devices on (100) wafers, the NFETS largely operate in velocity saturation resulting in a source-to-drain current that is independent of orientation. On the other hand, as shown in FIGS. 3A and 3B, PFETS on (100) orientation wafers are less likely to be in velocity saturation and thus would benefit from optimizing the choice of crystal orientation around inversion layer hole mobility and other considerations such as the desirability of having matching transistors. This is clear from FIG. 3B, which depicts the drift velocity versus the electric field, as measured in V/cm. At the rightmost section of FIG. 3B, the drift velocity vd equals the saturation velocity vsat. That is, the drift velocity saturates at high electric fields and thus becomes independent of the value of the electric field. To be more precise:   Vd  =                              μ          0                ⁢        E                              [                      1            +                                          (                                                                            μ                      0                                        ⁢                    E                                                        v                    sat                                                  )                            β                                ]                          1          /          β                      =          {                                                                                    μ                  0                                ⁢                E                ⁢                                  xe2x80x83                                ⁢                …                ⁢                                  xe2x80x83                                ⁢                E                            →              0                                                                                                            v                  sat                                ⁢                                  xe2x80x83                                ⁢                …                ⁢                                  xe2x80x83                                ⁢                E                            →              ∞                                          
where vd is the drift velocity, xcex2 is a constant depending upon whether you are dealing with holes or electrons, where xcex2=1 for holes and xcex2=2 for electrons in silicon, E is the electric field, xcexc0 to is the constant of proportionality between vd and E at low to moderate electric fields, and vsat is the limit or saturation velocity approached at high electric field values. FIG. 3B shows the desired operational points for both holes and electrons, with these points being below the velocity saturation E field value.
CMOS technology where the PMOS and NMOS transistors have matching characteristics would offer significant advantages. In current state-of-the-art CMOS technology on (100) crystal orientation orientations, the NMOS transistor has a much higher hole/electron mobility than the PMOS transistor. Even if the NMOS transistor is operating with velocity saturation, the PMOS transistor mobility on (100) surfaces is so low as to preclude velocity saturation. If the transistors are made the same size, then the switching characteristics are asymmetrical resulting in circuit timing problems and excess power distribution as depicted in FIGS. 4A-4B. FIG. 4A illustrates the time when both transistors are on. Note that the upslope time is greater than the downslope time, and thus the waveform is asymmetrical as are the current pulses shown in FIG. 4B. Not only does the asymmetrical switching slow circuit response, but a DC path exists from the power supply to ground during a significant portion of the slow switching transient resulting in excess power dissipation. If the PMOS transistors, as is often done, are made two to three times larger than the NMOS devices, then extra stray capacitances are introduced which tend to make efforts to improve the pull-up switching speed self defeating and to result in extra power dissipation. Moreover, such architecture does not effectively utilize chip area in circuit layouts.
The problems and disadvantages of the prior art have been addressed and mitigated by the present invention, which is directed to a method for forming NMOS and PMOS transistors on (111) crystal orientations, the transistors having matching characteristics, as well as the devices formed thereby. The method fabricates deep sub-micron CMOS (xe2x80x9cComplementary Metal Oxide Semiconductorxe2x80x9d) transistors where the surface mobilities are comparable and high such that both the NMOS and PMOS transistors can operate with velocity saturation. Because the saturation velocity of both holes and electrons is close to 107 cm/sec, both types of transistors will have similar current characteristics, or similar sized devices will have approximately equal drain current under similar voltage magnitudes.
The method includes the steps of cutting a wafer substrate along a (111) crystal plane and fabricating NMOS and PMOS transistors in the wafer substrate. CMOS technologies provide both n- and p-channel devices in one chip, at the expense of some increase in fabrication complexity and use of chip area as compared to simple NMOS transistors. The great advantage of CMOS digital circuits is that they may be designed for essentially zero power consumption in steady-state conditions for both logic states, i.e. off and on. Consequently, average power consumption is usually much smaller for CMOS than for NMOS devices. Silicon-gate CMOS offers significant improvements over metal-gate CMOS, which remains the cheapest form of CMOS. However, the present invention relies on silicon-gate CMOS, as this type of CMOS is particularly well-suited for LSI applications as it offers higher circuit density and higher speed performance.
The CMOS transistors formed by the present invention have the following composition. The CMOS transistors are fabricated as deep sub-micron devices on a (111) crystal plane orientation of a wafer. By deep sub-micron, it is meant that the size of the devices fabricated on the (111) surface are on the order of 0.5 microns in size or less.
Also, the present invention is directed to a DRAM or other memory circuit and memory module containing memory circuits formed with integrated circuits containing CMOS transistors fabricated on a (111) crystal plane orientation and to a processor based system employing such a memory module and/or memory circuit.